lh531000b cmos 1m (128k 8) mrom features 131,072 words 8 bit organization access time: 150 ns (max.) low power consumption: operating: 192.5 mw (max.) standby: 550 m w (max.) programmable ce/oe/ oe static operation ttl compatible i/o three-state outputs single +5 v power supply packages: 28-pin, 600 -mil dip 28-pin, 450 -mil sop mask rom specific pinout desc ription the lh531000b is a mask-programmable rom organized as 131,072 8 bits. it is fabricated using silicon-gate cmos process technology. pin connections 531000b-1 top view 28-pin dip 28-pin sop 1 2 3 4 7 8 a 2 a 5 26 25 24 23 22 21 18 15 a 7 a 6 5 6 a 3 a 4 20 19 a 15 a 12 gnd a 13 a 8 a 11 a 10 ce d 7 d 6 d 3 9 10 11 28 27 a 14 a 1 v cc 12 17 d 5 16 d 4 d 1 d 2 a 0 d 0 a 9 /oe/oe 13 14 a 16 figure 1. pin connections for dip and sop packages 1
note: 1. active level of ce/oe/ oe is mask-programmable. truth table pin 20 ce oe/ oe mode d 0 - d 7 supply current ce type l C selected d out operating (i cc ) h C non selected high-z standby (i sb ) oe type C h/l selected d out operating (i cc ) C l/h non selected high-z 531000b-2 a 3 a 2 a 1 a 12 a 11 a 10 a 9 a 8 28 2 23 21 24 4 7 8 9 a 7 a 6 v cc a 4 16 17 18 11 19 d 0 memory matrix (131,072 x 8) sense amplifier output buffer 14 3 gnd d 1 d 2 d 3 d 4 d 5 d 6 d 7 15 12 13 6 25 a 5 5 a 13 26 address buffer a 0 10 address decoder column selector ce/oe buffer a 14 27 a 15 1 20 timing generator a 16 22 ce/oe/oe figure 2. lh 531000b block diagram pin description signal pin name note a 0 - a 16 address input d 0 - d 7 data output ce/oe/ oe chip enable input or output enable input 1 signal pin name note v cc power supply (+5 v) gnd ground lh531000b cmos 1m mrom 2
absolute maximum ratings parameter symbol rating unit supply voltage v cc C0.3 to +7.0 v input voltage v in C0.3 to v cc +0.3 v output voltage v out C0.3 to v cc +0.3 v operating temperature topr 0 to +70 c storage temperature tstg C65 to +150 c recommended operating conditions (t a = 0 to +70 c) parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v dc characterist ics (v cc = 5 v 10%, t a = 0 to +70 c) parameter symbol con ditions min. typ. max. unit note input low voltage v il C0.3 0.8 v input high voltage v ih 2.2 v cc + 0.3 v output low voltage v ol i ol = 2.0 ma 0.4 v output high voltage v oh i oh = C400 m a 2.4 v input leakage current | i li | v in = 0 v to v cc 10 m a output leakage current | i lo |v out = 0 v to v cc 10 m a 1 operating current i cc1 t rc = 150 ns 35 ma 2 i cc2 t rc = 1 m s 25 i cc3 t rc = 150 ns 30 ma 3 i cc4 t rc = 1 m s20 standby current i sb1 ce = v ih 2ma i sb2 ce = v cc C 0.2 v 100 m a input capacitance c in f = 1 mhz t a = 25 c 10 pf output capacitance c out 10 pf notes: 1. ce/ oe = v ih, oe = v il 2. v in = v ih or v il , ce = v il , outputs open 3. v in = (v cc - 0.2 v) or 0.2 v. ce = 0.2 v, outputs open ac characterist ics (v cc = 5 v 10%, t a = 0 to +70 c) parameter symbol min. typ. max. unit note read cycle time t rc 150 ns address access time t aa 150 ns chip enable access time t ace 150 ns output enable time t oe 70 ns output hold time t oh 5ns ce to output in high-z t chz 70 ns 1 oe to output in high-z t ohz 70 ns note: 1. this is the time required for the output to become high-impe dance. cmos 1m mrom lh531000b 3
ac test conditions parameter rating input voltage amplitude 0.6 v to 2.4 v input rise/fall time 10 ns input reference level 1.5 v output reference level 0.8 v and 2.2 v output load condition 1ttl +100 pf t oe t aa a 0 - a 16 t ohz t chz d 0 - d 7 531000b-3 t rc t ace ce oe t oh data valid (note) (note) oe note: data becomes valid after t aa , t ace , and t oe from address input, chip enable, and output enable, respectively have been met. (note) figure 3. timing diagram lh531000b cmos 1m mrom 4
package diagrams dimensions in mm [inches] maximum limit minimum limit 28dip (dip028-p-0600) 114 15 28 28dip-2 13.45 [0.530] 12.95 [0.510] 0.51 [0.020] min. 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] typ. 0.60 [0.024] 0.40 [0.016] 0.30 [0.012] 0.20 [0.008] detail 36.30 [1.429] 35.70 [1.406] 0 to 15 4.50 [0.177] 4.00 [0.157] 15.24 [0.600] typ. 28-pin, 600-mil dip dimensions in mm [inches] maximum limit minimum limit 28sop (sop028-p-0450) 12.40 [0.488] 11.60 [0.457] 8.80 [0.346] 8.40 [0.331] 10.60 [0.417] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.10 [0.004] 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] typ. 28 15 14 1 1.70 [0.067] 1.70 [0.067] 28sop 28-pin, 450-mil sop cmos 1m mrom lh531000b 5
d 28-pin, 600-mil dip (dip028-p-0600) n 28-pin, 450-mil sop (sop028-p-0450) lh531000b device type x package 531000b-7 example: lh531000bd (cmos 1m (128k x 8) mask programmable rom, 28-pin, 600-mil dip) cmos 1m (128k x 8) mask programmable rom ordering information lh531000b cmos 1m mrom 6
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